Differences

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--- ff3:ff3us:doc:snes:register [2019/08/06 04:34]
madsiur [Signed Multiply Result]
+++ ff3:ff3us:doc:snes:register [2019/08/10 03:42] (current)
madsiur [PPU1 Status and Version Number]
@@ Line 63: / Line 63: @@
 |Signed Multiply Result (High)  |  [[register#Signed Multiply Result|$2136]]  |  MPYH  |  single  |  read  |  f-blank, v-blank, h-blank  |
 |Latch H/V-Counter by Software  |  [[register#Latch H/V-Counter by Software|$2137]]  |  SLHV  |  single  |    |  any time  |
-|OAM Data Read Register  |  ''$2138''  |  OAMDATAREAD  |  dual  |  read  |  f-blank, v-blank  |
+|OAM Data Read  |  [[register#OAM Data Read|$2138]]  |  RDOAM  |  dual  |  read  |  f-blank, v-blank  |
-|VRAM Data Read Register (Low)  |  ''$2139''  |  VMDATALREAD  |  single  |  read  |  f-blank, v-blank  |
+|VRAM Data Read (Low)  |  [[register#VRAM Data Read|$2139]]  |  RDVRAML  |  single  |  read  |  f-blank, v-blank  |
-|VRAM Data Read Register (High)  |  ''$213A''  |  VMDATAHREAD  |  single  |  read  |  f-blank, v-blank  |
+|VRAM Data Read (High)  |  [[register#VRAM Data Read|$213A]]  |  RDVRAMH  |  single  |  read  |  f-blank, v-blank  |
-|CGRAM Data Read Register  |  ''$213B''  |  CGDATAREAD  |  dual  |  read  |  f-blank, v-blank  |
+|CGRAM Data Read  |  [[register#CGRAM Data Read|$213B]]  |  RDCGRAM  |  dual  |  read  |  f-blank, v-blank  |
-|Scanline Location Registers (Horizontal)  |  ''$213C''  |  OPHCT  |  dual  |  read  |  any time  |
+|Horizontal Counter Latch  |  [[register#Counter Latch|$213C]]  |  OPHCT  |  dual  |  read  |  any time  |
-|Scanline Location Registers (Vertical)  |  ''$213D''  |  OPVCT  |  dual  |  read  |  any time  |
+|Vertical Counter Latch  |  [[register#Counter Latch|$213D]]  |  OPVCT  |  dual  |  read  |  any time  |
-|PPU Status Register  |  ''$213E''  |  STAT77  |  single  |  read  |  any time  |
+|PPU1 Status and Version Number  |  [[register#PPU1 Status and Version Number|$213E]]  |  STAT77  |  single  |  read  |  any time  |
-|PPU Status Register  |  ''$213F''  |  STAT78  |  single  |  read  |  any time  |
+|PPU2 Status and Version Number  |  [[register#PPU2 Status and Version Number|$213F]]  |  STAT78  |  single  |  read  |  any time  |
 |APU IO Registers  |  ''$2140''  |  APUIO0  |  single  |  both  |  any time  |
 |APU IO Registers  |  ''$2141''  |  APUIO1  |  single  |  both  |  any time  |
@@ Line 765: / Line 765: @@
 [[register#Address Bus B Registers|Back to top]]
+===== OAM Data Read =====
+<code>
+$2138 r w++?- RDOAM - Data for OAM read
+        xxxxxxxx = Byte to read from OAM
+</code>
+OAM reads are straightforward: the current byte as set in $2102-$2103 and incremented by reads from this register and writes to $2104 will be returned. Note that writes to the lower table are not affected so logically. OAM Size is $0220 bytes (addresses $0220..$03FF are mirrors of $0200h..$021F).
+[[register#Address Bus B Registers|Back to top]]
+===== VRAM Data Read =====
+<code>
+$2139 r l++?- RDVRAML - VRAM Data Read low byte
+$213A r h++?- RDVRAMH - VRAM Data Read high byte
+        xxxxxxxx xxxxxxxx = Word to read from VRAM
+</code>
+Reading from these registers returns the LSB or MSB of an internal 16 bit prefetch register. Depending on the Increment Mode the address does (or doesn't) get automatically incremented after the read. The prefetch register is filled with data from the currently addressed VRAM word (with optional Address Translation applied) upon two situations:
+<code>
+Prefetch occurs AFTER changing the VRAM address (by writing $2116-$2117).
+Prefetch occurs BEFORE incrementing the VRAM address (by reading $2139-$213A).
+</code>
+The "Prefetch BEFORE Increment" effect is some kind of a hardware glitch (Prefetch AFTER Increment would be more useful). Increment/Prefetch in detail:
+<code>
+st  Send a byte from OLD prefetch value to the CPU (always)
+nd  Load NEW value from OLD address into prefetch register (only if increment occurs)
+rd  Increment address so it becomes the NEW address (only if increment occurs)
+</code>
+Increments caused by writes to $2118-$2119 don't do any prefetching (the prefetch register is left totally unchanged by writes). In practice, after changing the VRAM address (via $2116-$2117), the first byte/word will be received twice, further values are received from properly increasing addresses (as a workaround, issue a dummy-read that ignores the 1st or 2nd value).
+[[register#Address Bus B Registers|Back to top]]
+===== CGRAM Data Read =====
+<code>
+$213B r w++?- RDCGRAM - CGRAM Data read
+        ubbbbbgg gggrrrrr
+        u     = unused (PPU2 open bus)
+        bbbbb = Blue Channel
+        ggggg = Green Channel
+        rrrrr = Red Channel
+</code>
+This reads from CGRAM. Accesses to CGRAM are handled just like accesses to the low table of OAM, see $2138 for details. Note that the color values are stored in BGR order. After the byte is read, the CGRAM address is incremented so that the next read will be to the following byte.
+[[register#Address Bus B Registers|Back to top]]
+===== Counter Latch =====
+<code>
+$213C r w++++ OPHCT - Horizontal Counter Latch
+$213D r w++++ OPVCT - Vertical Counter Latch
+        uuuuuuux xxxxxxxx
+        uuuuuuu   = unused (PPU2 Open Bus)
+        xxxxxxxxx = Scanline Location
+</code>
+These values are latched by reading $2137 when bit 7 of $4201 is set, or by clearing-and-setting bit 7 of $4201 either by writing $4201 or by pin 6 of Controller Port 2 (the latch occurs on the 1->0 transition). Note that the value read is only 9 bits: bits 1-7 of the high byte are PPU2 Open Bus. Each register keeps seperate track of whether to return the low or high byte. The high/low selector is reset to 'low' when $213F is read (the selector is NOT reset when the counter is latched). H Counter values range from 0 to 339, with 22-277 being visible on the screen. V Counter values range from 0 to 261 in NTSC mode (262 is possible every other frame when interlace is active) and 0 to 311 in PAL mode (312 in interlace?), with 1-224 (or 1-239(?) if overscan is enabled) visible on the screen.
+[[register#Address Bus B Registers|Back to top]]
+===== PPU1 Status and Version Number =====
+<code>
+$213E r b++++ STAT77 - PPU1 Status and Version Number
+        trmuvvvv
+        t    = OBJ Time overflow  (0=Okay, 1=More than 8x34 OBJ pixels per scanline)
+        r    = OBJ Range overflow (0=Okay, 1=More than 32 OBJs per scanline)
+        m    = Master/Slave Mode (PPU1.Pin25) (0=Normal=Master)
+        u    = unused
+        vvvv = PPU1 5C77 Version Number (only version 1 exists)
+</code>
+Bit t: If more than 34 sprite-tiles (e.g. a 16x16 sprite has 2 sprite-tiles) were encountered on a single line, this flag will be set. The flag is reset at the end of V-Blank but not during forced blank.
+Bit r: If more than 32 sprites were encountered on a single line, this flag will be set. The flag is reset at the end of V-Blank but not during forced blank.
+Note that the above two flags are set whether or not OBJ are actually enabled at the time (see $212C), at the following times: bit 6 when V=OBJ.YLOC/H=OAM.INDEX*2, bit 7 when V=OBJ.YLOC+1/H=0.
+[[register#Address Bus B Registers|Back to top]]
+===== PPU2 Status and Version Number =====
+<code>
+$213F r b++++ STAT78 - PPU2 Status and Version Number
+        flupvvvv
+        f    = Current Interlace-Frame (0=1st, 1=2nd Frame)
+        l    = H/V-Counter/Lightgun/Joypad2.Pin6 Latch Flag (0=No, 1=New Data Latched)
+        u    = unused
+        p    = Frame Rate (PPU2.Pin30)  (0=NTSC/60Hz, 1=PAL/50Hz)
+        vvvv = PPU2 5C78 Version Number (version 1..3)
+</code>