Differences

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--- ff3:ff3us:doc:snes:register [2019/08/06 03:23]
madsiur [Address Bus B Registers]
+++ ff3:ff3us:doc:snes:register [2019/08/10 03:42] (current)
madsiur [PPU1 Status and Version Number]
@@ Line 57: / Line 57: @@
 |Color Math Control Register A  |  [[register#Color Math Control Register A|$2130]]  |  CGWSEL  |  single  |  write  |  f-blank, v-blank, h-blank  |
 |Color Math Control Register B  |  [[register#Color Math Control Register B|$2131]]  |  CGADSUB  |  single  |  write  |  f-blank, v-blank, h-blank  |
-|Fixed Color Data  |  [[register#Fixed Color Data|$2132]]  |  COLDATA  |  single  |  write  |  f-blank, v-blank, h-blank  |
+|Color Math Subscreen Backdrop Color  |  [[register#Color Math Subscreen Backdrop Color|$2132]]  |  COLDATA  |  single  |  write  |  f-blank, v-blank, h-blank  |
-|Screen Mode Select Register  |  ''$2133''  |  SETINI  |  single  |  write  |  f-blank, v-blank, h-blank  |
+|Screen Mode / Video Select  |  [[register#Screen Mode / Video Select|$2133]]  |  SETINI  |  single  |  write  |  f-blank, v-blank, h-blank  |
-|Multiplication Result Registers  |  ''$2134''  |  MPYL  |  single  |  read  |  f-blank, v-blank, h-blank  |
+|Signed Multiply Result (Low)  |  [[register#Signed Multiply Result|$2134]]  |  MPYL  |  single  |  read  |  f-blank, v-blank, h-blank  |
-|Multiplication Result Registers  |  ''$2135''  |  MPYM  |  single  |  read  |  f-blank, v-blank, h-blank  |
+|Signed Multiply Result (Middle)  |  [[register#Signed Multiply Result|$2135]]  |  MPYM  |  single  |  read  |  f-blank, v-blank, h-blank  |
-|Multiplication Result Registers  |  ''$2136''  |  MPYH  |  single  |  read  |  f-blank, v-blank, h-blank  |
+|Signed Multiply Result (High)  |  [[register#Signed Multiply Result|$2136]]  |  MPYH  |  single  |  read  |  f-blank, v-blank, h-blank  |
-|Software Latch Register  |  ''$2137''  |  SLHV  |  single  |    |  any time  |
+|Latch H/V-Counter by Software  |  [[register#Latch H/V-Counter by Software|$2137]]  |  SLHV  |  single  |    |  any time  |
-|OAM Data Read Register  |  ''$2138''  |  OAMDATAREAD  |  dual  |  read  |  f-blank, v-blank  |
+|OAM Data Read  |  [[register#OAM Data Read|$2138]]  |  RDOAM  |  dual  |  read  |  f-blank, v-blank  |
-|VRAM Data Read Register (Low)  |  ''$2139''  |  VMDATALREAD  |  single  |  read  |  f-blank, v-blank  |
+|VRAM Data Read (Low)  |  [[register#VRAM Data Read|$2139]]  |  RDVRAML  |  single  |  read  |  f-blank, v-blank  |
-|VRAM Data Read Register (High)  |  ''$213A''  |  VMDATAHREAD  |  single  |  read  |  f-blank, v-blank  |
+|VRAM Data Read (High)  |  [[register#VRAM Data Read|$213A]]  |  RDVRAMH  |  single  |  read  |  f-blank, v-blank  |
-|CGRAM Data Read Register  |  ''$213B''  |  CGDATAREAD  |  dual  |  read  |  f-blank, v-blank  |
+|CGRAM Data Read  |  [[register#CGRAM Data Read|$213B]]  |  RDCGRAM  |  dual  |  read  |  f-blank, v-blank  |
-|Scanline Location Registers (Horizontal)  |  ''$213C''  |  OPHCT  |  dual  |  read  |  any time  |
+|Horizontal Counter Latch  |  [[register#Counter Latch|$213C]]  |  OPHCT  |  dual  |  read  |  any time  |
-|Scanline Location Registers (Vertical)  |  ''$213D''  |  OPVCT  |  dual  |  read  |  any time  |
+|Vertical Counter Latch  |  [[register#Counter Latch|$213D]]  |  OPVCT  |  dual  |  read  |  any time  |
-|PPU Status Register  |  ''$213E''  |  STAT77  |  single  |  read  |  any time  |
+|PPU1 Status and Version Number  |  [[register#PPU1 Status and Version Number|$213E]]  |  STAT77  |  single  |  read  |  any time  |
-|PPU Status Register  |  ''$213F''  |  STAT78  |  single  |  read  |  any time  |
+|PPU2 Status and Version Number  |  [[register#PPU2 Status and Version Number|$213F]]  |  STAT78  |  single  |  read  |  any time  |
 |APU IO Registers  |  ''$2140''  |  APUIO0  |  single  |  both  |  any time  |
 |APU IO Registers  |  ''$2141''  |  APUIO1  |  single  |  both  |  any time  |
@@ Line 702: / Line 702: @@
 [[register#Address Bus B Registers|Back to top]]
+===== Color Math Subscreen Backdrop Color =====
+<code>
+$2132  wb+++- COLDATA - Fixed Color Data
+        bgrccccc
+        b     = Apply Blue  (0=No change, 1=Apply Intensity as Blue)
+        g     = Apply Green (0=No change, 1=Apply Intensity as Green)
+        r     = Apply Red   (0=No change, 1=Apply Intensity as Red)
+        ccccc = Intensity (0..31)
+</code>
+The Subscreen Backdrop Color is used when all sub screen layers are disabled or transparent, in this case the "Div2" Half Color Math isn't applied (i.e. $2131 bit 6 is ignored). There is one exception, if "Sub Screen BG/OBJ Enable" is off ($2130 bit 1 = 0), then the "Div2" isn't forcefully ignored. For a FULLY TRANSPARENT backdrop, set this register to Black (adding or subtracting black has no effect, and, with "Div2" disabled/ignored, the raw Main screen is displayed as is).
+[[register#Address Bus B Registers|Back to top]]
+===== Screen Mode / Video Select =====
+<code>
+$2133  wb+++- SETINI - Screen Mode/Video Select
+        seuupoIi
+        s  = External Synchronization (0=Normal, 1=Super Impose and etc.)
+        e  = EXTBG Mode (Screen expand)
+        uu = unused
+        p  = Horizontal Pseudo 512 Mode (0=Disable, 1=Enable) (shift Subscreen half dot to the left)
+        o  = BG V-Direction Display (0=224 Lines, 1=239 Lines) (for NTSC/PAL)
+        I  = OBJ V-Direction Display (0=Low, 1=High Resolution/Smaller OBJs)
+        i  = V-Scanning (0=Non Interlace, 1=Interlace) (See Port $2105)
+</code>
+Bit s: Used for superimposing "sfx" graphics, whatever that means. Usually 0. Not much is known about this bit. Interestingly, the SPPU1 chip has a pin named "EXTSYNC" (or not-EXTSYNC, since it has a bar over it) which is tied to Vcc.
+Bit e: When this bit is set, you may enable BG2 on Mode 7. BG2 uses the same tile and character data as BG1, but interprets the high bit of the color data as a priority for the pixel. Various sources report additional effects for this bit, possibly related to bit 7. For example, "Enable the Data Supplied From the External Lsi.", whatever that means. Of course, maybe that's a typo and it's supposed to apply to bit 7 instead.
+Bit p: This creates a 512-pixel horizontal resolution by taking pixels from the Subscreen for the even-numbered pixels (zero based) and from the main screen for the odd-numbered pixels. Color math behaves just as with Mode 5/6 hires. The interlace bit still has no effect. Mosaic operates as normal (not like Mode 5/6). The Subscreen pixel is clipped (by windows) when the main-screen pixel to the LEFT is clipped, not when the one to the RIGHT is clipped as you'd expect. What happens with pixel column 0 is unknown. Enabling this bit in Modes 5 or 6 has no effect.
+Bit o: When set, 239 lines will be displayed instead of the normal 224. This also means V-Blank will occur that much later, and be shorter. All that happens is that extra lines get added to the display, and it seems the TV will like to move the display up 8 pixels. Overscan: The bit only matters at the very end of the frame, if you change the setting on line 0xE0 before the normal NMI trigger point then it's the same as if you had it on all frame. Note that this affects both the NMI trigger point and when HDMA stops for the frame. If you turn the bit off at the very beginning of scanline X (for 0xE1<=X<=0xF0), NMI will occur on line X and the last HDMA transfer will occur on line X-1. However, the display will remain in the normal no-overscan position for lines E1-EC, it will move up only one pixel for line ED, and it will lose vertical sync for lines EF-F4! Turning the bit on, only line E1 gives any effect: NMI will occur on line E2, although the last HDMA will still occur on line E0. Anything else acts like you left the bit off the whole time. Note, however, that if you wait too long after the beginning of the scanline then you will get no effect.
+Bit I: When set regardless of BG mode, the OBJ will be interlaced (see bit 0 below), and thus will appear half-height. Note that this only controls whether obj are drawn as normal or not, the interlace signal is only output to the TV based on bit 0 below.
+Bit i: When set in BG mode 5 (and probably 6), the effective screen height will be 448 (or 478) pixels, rather than 224 (or 239). When set in any other mode, the screen will just get a bit jumpy. However, toggling the tilemap each field would simulate the increased screen height (much like pseudo-hires simulares hires). In hardware, setting this bit makes the SNES output a normal interlace signal rather than always forcing one frame.
+[[register#Address Bus B Registers|Back to top]]
+===== Signed Multiply Result =====
+<code>
+$2134 r l+++? MPYL - Signed Multiplication Result low byte
+$2135 r m+++? MPYM - Signed Multiplication Result middle byte
+$2136 r h+++? MPYH - Signed Multiplication Result high byte
+        xxxxxxxx xxxxxxxx xxxxxxxx = Signed Multiplication Result
+</code>
+This is the 2's compliment product of the 16-bit value written to $211B and the 8-bit value most recently written to $211C. There is supposedly no important delay. It may not be operative during Mode 7 rendering.
+[[register#Address Bus B Registers|Back to top]]
+===== Latch H/V-Counter by Software =====
+<code>
+$2137   b++++ SLHV - Software Latch for H/V Counter
+        uuuuuuuu = unused (CPU Open Bus; usually last opcode)
+</code>
+Reading from this register latches the current H/V counter values into OPHCT/OPVCT ($213C-$213D) if bit 7 of $2101 is set. The data actually read is open bus.
+[[register#Address Bus B Registers|Back to top]]
+===== OAM Data Read =====
+<code>
+$2138 r w++?- RDOAM - Data for OAM read
+        xxxxxxxx = Byte to read from OAM
+</code>
+OAM reads are straightforward: the current byte as set in $2102-$2103 and incremented by reads from this register and writes to $2104 will be returned. Note that writes to the lower table are not affected so logically. OAM Size is $0220 bytes (addresses $0220..$03FF are mirrors of $0200h..$021F).
+[[register#Address Bus B Registers|Back to top]]
+===== VRAM Data Read =====
+<code>
+$2139 r l++?- RDVRAML - VRAM Data Read low byte
+$213A r h++?- RDVRAMH - VRAM Data Read high byte
+        xxxxxxxx xxxxxxxx = Word to read from VRAM
+</code>
+Reading from these registers returns the LSB or MSB of an internal 16 bit prefetch register. Depending on the Increment Mode the address does (or doesn't) get automatically incremented after the read. The prefetch register is filled with data from the currently addressed VRAM word (with optional Address Translation applied) upon two situations:
+<code>
+Prefetch occurs AFTER changing the VRAM address (by writing $2116-$2117).
+Prefetch occurs BEFORE incrementing the VRAM address (by reading $2139-$213A).
+</code>
+The "Prefetch BEFORE Increment" effect is some kind of a hardware glitch (Prefetch AFTER Increment would be more useful). Increment/Prefetch in detail:
+<code>
+st  Send a byte from OLD prefetch value to the CPU (always)
+nd  Load NEW value from OLD address into prefetch register (only if increment occurs)
+rd  Increment address so it becomes the NEW address (only if increment occurs)
+</code>
+Increments caused by writes to $2118-$2119 don't do any prefetching (the prefetch register is left totally unchanged by writes). In practice, after changing the VRAM address (via $2116-$2117), the first byte/word will be received twice, further values are received from properly increasing addresses (as a workaround, issue a dummy-read that ignores the 1st or 2nd value).
+[[register#Address Bus B Registers|Back to top]]
+===== CGRAM Data Read =====
+<code>
+$213B r w++?- RDCGRAM - CGRAM Data read
+        ubbbbbgg gggrrrrr
+        u     = unused (PPU2 open bus)
+        bbbbb = Blue Channel
+        ggggg = Green Channel
+        rrrrr = Red Channel
+</code>
+This reads from CGRAM. Accesses to CGRAM are handled just like accesses to the low table of OAM, see $2138 for details. Note that the color values are stored in BGR order. After the byte is read, the CGRAM address is incremented so that the next read will be to the following byte.
+[[register#Address Bus B Registers|Back to top]]
+===== Counter Latch =====
+<code>
+$213C r w++++ OPHCT - Horizontal Counter Latch
+$213D r w++++ OPVCT - Vertical Counter Latch
+        uuuuuuux xxxxxxxx
+        uuuuuuu   = unused (PPU2 Open Bus)
+        xxxxxxxxx = Scanline Location
+</code>
+These values are latched by reading $2137 when bit 7 of $4201 is set, or by clearing-and-setting bit 7 of $4201 either by writing $4201 or by pin 6 of Controller Port 2 (the latch occurs on the 1->0 transition). Note that the value read is only 9 bits: bits 1-7 of the high byte are PPU2 Open Bus. Each register keeps seperate track of whether to return the low or high byte. The high/low selector is reset to 'low' when $213F is read (the selector is NOT reset when the counter is latched). H Counter values range from 0 to 339, with 22-277 being visible on the screen. V Counter values range from 0 to 261 in NTSC mode (262 is possible every other frame when interlace is active) and 0 to 311 in PAL mode (312 in interlace?), with 1-224 (or 1-239(?) if overscan is enabled) visible on the screen.
+[[register#Address Bus B Registers|Back to top]]
+===== PPU1 Status and Version Number =====
+<code>
+$213E r b++++ STAT77 - PPU1 Status and Version Number
+        trmuvvvv
+        t    = OBJ Time overflow  (0=Okay, 1=More than 8x34 OBJ pixels per scanline)
+        r    = OBJ Range overflow (0=Okay, 1=More than 32 OBJs per scanline)
+        m    = Master/Slave Mode (PPU1.Pin25) (0=Normal=Master)
+        u    = unused
+        vvvv = PPU1 5C77 Version Number (only version 1 exists)
+</code>
+Bit t: If more than 34 sprite-tiles (e.g. a 16x16 sprite has 2 sprite-tiles) were encountered on a single line, this flag will be set. The flag is reset at the end of V-Blank but not during forced blank.
+Bit r: If more than 32 sprites were encountered on a single line, this flag will be set. The flag is reset at the end of V-Blank but not during forced blank.
+Note that the above two flags are set whether or not OBJ are actually enabled at the time (see $212C), at the following times: bit 6 when V=OBJ.YLOC/H=OAM.INDEX*2, bit 7 when V=OBJ.YLOC+1/H=0.
+[[register#Address Bus B Registers|Back to top]]
+===== PPU2 Status and Version Number =====
+<code>
+$213F r b++++ STAT78 - PPU2 Status and Version Number
+        flupvvvv
+        f    = Current Interlace-Frame (0=1st, 1=2nd Frame)
+        l    = H/V-Counter/Lightgun/Joypad2.Pin6 Latch Flag (0=No, 1=New Data Latched)
+        u    = unused
+        p    = Frame Rate (PPU2.Pin30)  (0=NTSC/60Hz, 1=PAL/50Hz)
+        vvvv = PPU2 5C78 Version Number (version 1..3)
+</code>