Introduction

This is a list of the opcodes used in the 65816 processor. It is used by the Super Nintendo System (SNES) console.

For the registers, the following convention will be used:

For the opcode arguments, the following convention will be used:

Reads a value from the memory and stores it in the specified register. LDA will store in the A or C register, LDX will store in the X register and LDY will store in the Y register.

Reads a value from the specified register and stores it in the memory. STA will read the A or C register, STX will read the X register and STY will read the Y register. All opcodes will store the retrieved value in the specified address.

The STZ opcode will always store the value of zero in the designed memory address. Unlike the STA, STX and STY opcodes, the STZ opcode doesn't affect flags. It also doesn't affect the A or C register.

Test all bits in the A or C register. For all bits set in the A or C register, the correspondent bits will be set or unset in the designed memory address. TSB will set the correspondent bits and TRB will reset the correspondent bits. All clear bits in the A or C register will be ignored and their correspondent bits in the designed address will not be altered.

Add or subtract the value in the A or C register with the value in the designed memory address. ADC will add the value and SBC will subtract the value.

When the carry flag is set, a value of one will be added in the addition or subtraction operation.

The operation can overflow or underflow. It is the coder responsibility to check these cases and adjust the resulting value. A common method is to check the carry flag for overflow or underflow and cap the value to a prefixed setting.

Increment or decrement the specified register by one. It is equivalent to the ADC or SBC opcodes with the value of one without the carry flag set.

INC will increment the A or C register. INX will increment the X register. INY will increment the Y register. DEC will decrement the A or C register. DEX will decrement the X register. DEY will decrement the Y register. The operation can underflow or overflow.

INC and DEC can also increment or decrement a value in memory instead of the A or C register.

A binary operation is done between the register A or C and the memory. The AND opcode will do a binary AND, the ORA opcode will do a binary OR and the EOR opcode will do a binary XOR. The result will be stored in the A or C register.

Does a binary AND between the A or C register and the memory. Unlike the AND opcode, the binary AND operation doesn't alter the A or C register.

Compare the designed register with the memory and sets flags based on the comparison. CMP will compare the A or C register, CPX will compare the X register and CPY will compare the Y register. Generally, a conditional branch opcode, based on a flag status, is used after these opcodes.

Shift bits in the designed register or memory address left or right. The LSR opcode will shift the bits right and the ASL opcode will shift the bits left.

LSR is equivalent to divide the number by two and ASL is equivalent to multiply the number by two. The operation can underflow or overflow. The bit shifted out will become the new carry. The bit shifted in is zero.

Shift bits in the designed register or memory address left or right. The ROL opcode will shift the bits left and the ROR opcode will shift the bits right.

The bit shifted in is the old carry. The bit shifted out will be the new carry.

Change the execution flow based on a conditional branch. If the condition is meet, the execution flow will be changed for the designed address. Otherwise, it continues normally.

The majority of the conditional branches are based in flag status. The flags were setup by anterior opcodes.

Change the execution flow to the designed address.

Calls a sub routine which will be executed.

The JSR opcode will put two bytes in the stack, relative to the return address. It is expected that they will be retrieved by an RTS opcode in the sub routine.

The JSL opcode will put three bytes in the stack, relative to the return address. It is expected that they will be retrieved by an RTL opcode in the sub routine.

RTS will pull two bytes from the stack and RTL will pull three bytes from the stack. They will be setup as the new control flow address.

It is expected that the bytes in the stack were pushed from a JSR opcode for the RTS opcode and from a JSL opcode for the RTL opcode.

Set or reset flags.

Transfer bytes between the specified registers or special addresses.

If the setting of the registers have different settings of 8-bit or 16-bit, the copy of the high byte of the transfer can be truncated based on the opcode behavior.

Move a block of bytes from a specified address to another address. The X register will be the start address to copy from. The Y register will be start address to copy to. The C register will be the number of bytes to copy minus one.

The opcode arguments are the source bank and the destination bank, in this order.

MVP must be used if the Y register is greater than the X register. Otherwise, MVN must be used instead.

Push bytes in the stack, based on the opcodes arguments. They always work in 16-bit mode.

Push or pull bytes from the stack. The setting of the register or special address as 8-bit or 16-bit will set the number of bytes pushed/pulled from the stack.

Does absolutely nothing. It is mostly used to waste cycles. A few special registers or addresses can't be fetch until a minimum number of cycles has passed.

If the coder needs to erase a code segment, for better performance, a branch or jump is recommended instead of a long line of NOP opcodes.

Setups the processor flags with the opcode argument. For each bit set in the argument, the correspondent flag is set or reset. REP will reset the flags and SEP will set the flags.

Exchanges the A and B registers.

Exchanges the carry flag and the emulation flag.